The present invention relates to a system wherein one or more host processors, each having one or more input-output channels, communicate through one or more storage control units to utilize data recorded on a plurality of disk drives. More particularly, the present invention provides a cache/disk subsystem including one or more storage control units and one or more cache storage units. The cache store is transparent to the user who programs the processor as though he were directly addressing the disk drives.
In data processing systems having extremely large electronic memories, it is well known to provide a smaller cache memory having a much faster access time than the main memory. When the processor issues a main memory address, this address is utilized to access an address descriptor table which is normally set associative and contains words identifying which main memory addresses are present in the cache memory. Each entry in the table also includes information identifying certain characteristics of the data at the associated addresses. If the addressed data is present in the cache memory then a transfer is set up between the processor and the cache memory. If the data being addressed is not present in the cache memory then it is retrieved from the main memory, entered into the cache memory, and then accessed for transfer to the processor.
Since the cache memory may be full at the time it is required to obtain further data from the main memory, provision is normally made for returning to the main memory some of the modified data in the cache memory. A common practice has been to assign a most recently used age to data as it is brought into the cache memory and to increment this age as other data is utilized. When it is necessary to read data out of the cache memory to make room for more data, then the data with the least recently used age is selected for return to the main memory.
In systems of the type described above, when a transfer is made from the main memory to the cache store it involves not only the data at the specific address called for by the processor, but the data at adjacent addresses on the assumption that the data most likely to be requested next will be in these adjacent addresses. Thus, transfers between the main memory and the cache memory are usually a fixed number of words called a segment.
While systems of the type described above have found wide use where the main memory consists of program instructions and operands where locality of reference is well known, and some use has been made of the concept where file memory contents are sequential data files, no caching has been made with system transparency against files which may be non-sequential. This invention provides exploitation of locality of reference to files even though they may not be sequential.